Senior FPGA Validation Engineer (Xilinx Vivado)

Overview

Senior FPGA Validation Engineer (Xilinx Vivado) We are hiring Engineers! | Talent Acquisition @ UST Responsibilities

Perform FPGA hardware testing. Pre silicon validation via FPGA for emulating the targeted IP sub-system. Post silicon validation, lab bring up and debug of the targeted IP sub-system. Root cause analysis and resolving issues encountered either in pre-silicon or post-silicon targeted IP sub-system. Requirements

Possess at least 3-4 years of relevant experiences. Willing to relocate and work onsite in Penang, Malaysia. Requires experience and demonstrated technical expertise in the development & execution of platform level functional test plans. Platform level experience with high speed I/O interfaces. Experienced in FPGA development, Synthesis with logical & physical constraints, Timing closure and Place and Route (PnR) in FPGA. Requires experience and demonstrated technical expertise in the domain of High speed I/O interfaces of computer system. Requires good written and oral communication skills; Demonstrate the ability to communicate with a variety of engineering disciplines and management. Familiarity with Xilinx reference platforms such as Zynq reference board etc. Seniority level

Mid-Senior level Employment type

Full-time

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Information :

• Company : UST Global
• Position : Senior FPGA Validation Engineer (Xilinx Vivado)
• Location : Bayan Lepas, Penang
• Country : MY