Senior Staff Engineer Digital Layout

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Senior Staff Engineer Digital Layout

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Infineon Technologies 3 days ago Be among the first 25 applicants Join to apply for the

Senior Staff Engineer Digital Layout

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Infineon Technologies Get AI-powered advice on this job and more exclusive features. All aspects of RTL2GDS physical implementation for block or full chip level Working alongside within local team and other functional teams and different development sites to ensure on time delivery and high-quality results Possess strong hands-on working knowledge of deep sub-micron ASIC implementation Wide experience with industry standard EDA tools for digital implementation and signoff (Synopsys DC/ICC/ICC2/PrimeTime, Cadence RC/Genus/Innovus/Tempus) Proven responsibility for full design flow from constraints write up to design closure and tapeout Floor planning and power planning. Placement, Clock tree synthesis, routing Design optimization, layout verification, and timing closure. Solid team player. Proactive and highly self -driven. Proven problem solving, debug and organisational skills. Experience with TCL/PERL scripting and flow automation to improve flow QoR and reduce TAT.

Job Description

In your new role you will:

All aspects of RTL2GDS physical implementation for block or full chip level Working alongside within local team and other functional teams and different development sites to ensure on time delivery and high-quality results Possess strong hands-on working knowledge of deep sub-micron ASIC implementation Wide experience with industry standard EDA tools for digital implementation and signoff (Synopsys DC/ICC/ICC2/PrimeTime, Cadence RC/Genus/Innovus/Tempus) Proven responsibility for full design flow from constraints write up to design closure and tapeout Floor planning and power planning. Placement, Clock tree synthesis, routing Design optimization, layout verification, and timing closure. Solid team player. Proactive and highly self -driven. Proven problem solving, debug and organisational skills. Experience with TCL/PERL scripting and flow automation to improve flow QoR and reduce TAT.

Your Profile

You are best equipped for this task if you have:

Bachelor or Master Degree in Electronics Engineering or similar discipline At least 5 years+ of professional experience in RTL2GDS physical implementation and verification Profound understanding of Synopsys Tool chain (Fusion Compiler, ICC2, Prime time, DC) Knowledge within Cadence Tool chain (Innovus, Tempus, Genus) as a plus Profound RTL2GDS knowledge with main focus on full Digital physical implementation flow and understanding with TCL-, Perl-, Python- writing Good communication skills and good initiative at work Ability to work with multi-cultural teams with strong drive to excel Preferred Skills: RTL Synthesis and Implementation Logical equivalence Static timing analysis Low power design implementation Power analysis and IR drop signoff Layout verification

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener.

Are you in?

We are on a journey to create the best Infineon for everyone.

This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.

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Seniority level Mid-Senior level Employment type

Employment type Full-time Job function

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Information :

• Company : Infineon Technologies
• Position : Senior Staff Engineer Digital Layout
• Location : George Town, Penang
• Country : MY